As semiconductor wafers progress to higher density chips with shrinking geometries, the materials and processes used in wafer fabrication are changing. At the same time, each chip has literally tens of billions of electrical connections between the various metal layers and silicon devices. Electrical performance is improved though concurrent scaling of device features.
Multiple conductive and insulating layers are required to enable the interconnection and isolation of devices on different layers. The interlayer dielectric (“ILD”) serves as an insulator material between each metal layer or between a first metal layer and the wafer. ILDs can be made of a low-k insulating material, such as SiLK. ILDs have many small vias, which are openings in the ILD that provide an electrical pathway from one metal layer to an adjacent metal layer. Metal layers can be made of copper. Vias are filled with a conductive metal, traditionally tungsten and more recently copper.
In interconnect structures, the connecting vias between metal layers are subject to significant thermo-mechanical stresses that can result in, for example, thermal-cycle and via resistance shift failures. Thermo-mechanical stress can occur when the thermal expansion coefficient of copper is less than that of the ILD materials. This is particularly true when the via chain structure includes a via that is relatively isolated, as in plate-below and Difmac 100 via chain structures. A plate-below via chain structure includes copper metal lines that are, for example, greater than or equal to 0.8 μm in width, at a lower line level that is connected by vias to an upper line level that has copper metal lines that are, for example, less than or equal to 0.8 μm in width. A Difmac 100 via chain structure includes metal lines with a width, for example, greater than or equal to 0.8 μm, at both the upper and lower line levels which are connected by vias that have a diameter, for example, less than or equal to 0.2 μm. Conversely, structures, such as the ground-rule via chain, that have a high via density experience fewer such failures. Additionally, recent modeling work has indicated that via stress increases as via density decreases. Modeled stress in vias has been correlated with thermal cycle failures and it follows that a higher via density favors thermal-cycle reliability.
The use of via fill patterns and line fill patterns has been suggested as a possible modification to decrease thermal cycle failures. However, this solution would have to be modified in order to address large metal pads with isolated vias.
It is therefore desirable to provide a solution that can avoid thermo-mechanical stress on vias and related failures, while also maintaining an economical via density. Exemplary embodiments of the present invention can provide a via-to-metal area ratio at least as large as a predetermined value below which the additional stress on the vias does not significantly increase.